1. Field of the Invention
The present invention relates to the manufacturing method of a photoelectric conversion device.
2. Description of the Related Art
As shown in FIG. 1 of Japanese Patent Laid-Open No. 2005-123517, installing an n-layer 104 that is an n-type semiconductor region for accumulating charges and a p-layer 105 that is a p-type semiconductor region on that n-layer 104 in a photodiode of a solid-state imaging device is described in Japanese Patent Laid-Open No. 2005-123517. According to Japanese Patent Laid-Open No. 2005-123517, it is possible to suppress dark current on the light-receiving surface of the photodiode by this structure.
Installing a bypass region 106 that continuously extends from the n-layer 104 to the bottom of the gate region 103 (control electrode) of a transfer MOS transistor is disclosed in Japanese Patent Laid-Open No. 2005-123517. The width of this bypass region 106 is controlled by implanting BF2 ions diagonally (at an implantation angle of θ=7°) using a photoresist 609 and control electrode 603 as masking materials, as shown in FIG. 4 of Japanese Patent Laid-Open No. 2005-123517. Alternatively, the width of this bypass region 106 is controlled by implanting BF2 ions diagonally (at an implantation angle of θ=7°) using a photoresist 1109, control electrode 1103 and side spacer 1111 as masking materials, as shown in FIG. 6 of Japanese Patent Laid-Open No. 2005-123517. By this, according to Japanese Patent Laid-Open No. 2005-123517, the process precision of the bypass region can be improved.
As shown in FIG. 5(b) of Japanese Patent Laid-Open No. 2008-041726, introducing an n-type impurity to form a photodiode semiconductor region 33 after forming gate electrodes 31, 32 in a pixel array region 101 and a gate region 42 in a peripheral circuit region 102 is described in Japanese Patent Laid-Open No. 2008-041726. After that, a p-type impurity is introduced and a surface p-type region 35 for structuring the photodiode to be embedded is formed. Furthermore, an n-type impurity is introduced by ion implantation using a gate electrode as a masking material, and semiconductor regions 3, 34, 44 comprising a portion of a source and drain are formed.
As shown in FIG. 5(c) of Japanese Patent Laid-Open No. 2008-041726, forming a silicon nitride film 36 so as to cover a pixel array region 101 and peripheral circuit region 102, and forming a silicon oxide film 37 thereon is described in Japanese Patent Laid-Open No. 2008-041726.
Furthermore, as shown in FIG. 5(d) of Japanese Patent Laid-Open No. 2008-041726, forming a side spacer on the side face of the gate electrode 42 in the peripheral circuit region 102 by etching the silicon nitride film 36 and silicon oxide film 37 in the peripheral circuit region 102 is described in Japanese Patent Laid-Open No. 2008-041726. At this time, a silicon nitride film 36 and silicon oxide film 37 remain on the entire surface of the pixel array region 101. By this, it is possible to widen the width of the potential grading layer of the MOS transistor in the pixel array region, and also thin the width of the potential grading layer of the MOS transistor in the peripheral circuit region 102. As a result, according to Japanese Patent Laid-Open No. 2008-041726, it is possible to achieve both suppression of characteristic degradation due to a hot carrier of a MOS transistor in the pixel array region, and realization of high-drive performance of a MOS transistor in the peripheral circuit region.
In Japanese Patent Laid-Open No. 2005-123517, forming a side spacer 1111 by coating the entire surface of a semiconductor with a film formed from SiO or SiN, and thereafter performing etching to leave only a predetermined portion is described. Specifically, a side spacer 1111 such as that shown in FIG. 6(b) of Japanese Patent Laid-Open No. 2005-123517 is formed by performing etching in a state in which a photodiode is protected by masking using a film made of SiO or SiN and a photoresist, as shown in FIG. 7 of Japanese Patent Laid-Open No. 2005-123517. By this, according to Japanese Patent Laid-Open No. 2005-123517, it is possible to suppress dark current that occurs in the photodiode.
However, in the technique of Japanese Patent Laid-Open No. 2005-123517, there is a possibility that the photodiode sustains etching damage when removing the film that masks the photodiode or the photoresist by etching after the process to form the side spacer 1111 is finished.
Incidentally, with the increase in the number of pixels in an imaging device such as a CMOS sensor, there is a demand for a reduction in chip area. Accordingly, there is a demand for a finer peripheral circuit (a MOS transistor in the peripheral region). In contrast to this, in a pixel array region in which a plurality of pixels are arranged, an improvement in the charge transfer efficiency from the photodiode to a floating diffusion unit by a transfer transistor is prioritized over fineness of pixel dimension. Here, a case in which the photodiode is comprised of a charge accumulation region including an n-type impurity for accumulating charges and a protection region including a p-type impurity and arranged on that charge accumulation region is considered. In order to achieve both a reduction in dark current in the photodiode and an improvement in the charge transfer efficiency by the transfer MOS transistor, there is a necessity to form a protection region at a position on the charge accumulation region having an appropriate offset from the gate electrode of the transfer MOS transistor.
Supposing this offset is too small, the potential barrier due to the protection region poses as an impediment when charges accumulated in the charge accumulation region travels toward the channel region of the transfer MOS transistor, and the charge transfer efficiency decreases. Supposing this offset is too large, the portion of the charge accumulation region (including a n-type layer and a bypass region) exposed to the surface of the semiconductor substrate widens, and the amount of dark current in the photodiode increases. Therefore, this offset must be finely controlled to a value determined to achieve both a reduction in dark current in the photodiode and an improvement in the charge transfer efficiency of the transfer MOS transistor.
There is no description relating to a method of improving the control precision of the offset of the surface p-type region from the gate electrode 31 of the transfer MOS transistor in Japanese Patent Laid-Open No. 2008-041726.